library ieee;
use ieee.std_logic_1164.all;

entity jkFlipFlop is
	port (
		j : in bit;
		k : in bit;
		clk : in bit;
		q, qnot : out bit
	);
end entity jkFlipFlop;

architecture DATAFLOW of jkFlipFlop is
	
	signal and1 : bit;
	signal and2 : bit;
	signal nor1 : bit;
	signal nor2 : bit;
	signal out0, outnot : bit;
	
begin

	and1 <= j and (clk and nor1);
	and2 <= k and (clk and nor2);
	nor1 <= and1 nor outnot;
	nor2 <= and2 nor out0;
	q <= out0;
	qnot <= outnot;

end architecture DATAFLOW;

architecture STRUCTURAL of jkFlipFlop is
	
	component nand3
	
	port(a,b,c : in bit;
		z : out bit
	);
	
	end component;
	
	component nand2
	  
	port(a,b : in bit;
		z : out bit
	);
	
	end component; 
		
	for all : nand3 use entity work.NAND3;
	for all : nand2 use entity work.NAND2;
	
	signal sigVec : bit_vector(3 downTo 0);
	
	
begin

	NAND3_0 : nand3  port map(j, clk, sigVec(3), sigVec(0));
	NAND3_1 : nand3 port map(k, clk, sigVec(2), sigVec(1));	
	NAND2_0 : nand2 port map(sigVec(0), sigVec(3), sigVec(2));
	NAND2_1 : nand2 port map(sigVec(1), sigVec(2), sigVec(3)); 
	
	q <= sigVec(2);
	qnot <= sigVec(3);
	
end architecture STRUCTURAL;